Enhanced word line driver to reduce gate capacitance for low voltage applications

ABSTRACT

An enhanced word line driver circuit suitable for use on integrated circuits such as flash memory devices with voltage boosting includes a load reduction circuit. In response to a boosted voltage, the load reduction circuit decouples a gate capacitance load of deselected enhanced word line drivers from the boost voltage generator. The reduction of capacitive loading decreases power consumption and shortens the voltage boost time of the memory device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to word line drivers powered by a powersupply with limited current driving ability, such as a charge pump, inintegrated circuit memory devices; and specifically to memory devicesincluding word line drivers powered with a boosted voltage during a readmode.

2. Description of the Related Art

Decreased power consumption and faster operating speeds are continuingtrends in integrated circuit design. Lower voltages generally result inlower power operation. Standards are emerging that power integratedcircuits at voltages lower than the typical 5 volts at present. Forexample, one low supply voltage which is emerging as a standard isspecified to operate over a range of about 2.7 to 3.6 volts. Other, evenlower supply potential standards are emerging. Low voltage supply rangesfall short of voltages needed for important applications. For example,in semiconductor memory devices, such as flash EEPROM or ROM, word linesmay operate at a read potential of 4 volts or more. Voltage supplyboosting circuitry is included on the integrated circuit to supply therequired on chip voltages. Such boosting circuits have limited currentdriving capability, and thus limit the speed of devices.

The performance of boosting circuits is also limited by capacitance,which includes parasitic capacitance and the capacitance of driverswhich rely on the boosted voltage. During a voltage boosting step,capacitance delays the voltage boost operation and increases the powerrequired from the voltage boost circuits. Some major sources ofcapacitance are well capacitance, interconnect capacitance, oxidecapacitance, and junction capacitance. Accordingly, it is desirable toprovide a circuit for use with integrated circuits that decreasescapacitance generally, and particularly decreases the capacitive load onthe boosted voltage source during voltage boost operations.

SUMMARY OF THE INVENTION

An enhanced word line driver is disclosed that reduces capacitance forvoltage boosting applications. Capacitance for low voltage applicationsis reduced by a load reduction circuit in the enhanced word line driver,implemented in an integrated circuit that includes a memory array. Theload reduction circuit reduces the capacitive load placed by deselectedword line drivers on the voltage boost source, particularly when themagnitude of the output of the voltage boost source increases.

The word line driver circuit includes a voltage source, a drivercircuit, a feedback circuit, and a load reduction circuit. The voltagesource supplies a first voltage. The driver circuit has an input, a twopower inputs, and an output. The output is coupled to a word line. Thefirst power input is coupled to the voltage source. In a selected mode,the word line driver circuit couples the word line to the first powerinput. In a deselected mode, the word line driver circuit couples theword line to the second power input. The feedback circuit has an input,an output, and a power input. The input of the feedback circuit iscoupled to the output of the driver circuit. The power input of thefeedback circuit is coupled to the voltage source. The load reductioncircuit has an input, an output, and a control input. The input of theload reduction circuit is coupled to the output of the feedback circuit.The output of the load reduction circuit is coupled to the input of thedriver circuit. In the deselected mode, the load reduction circuitreduces a capacitive load of the driver circuit on the voltage source.

In a second embodiment of the invention, an integrated circuit memorydevice includes a memory array, a plurality of address inputs, a voltagesource, a decoder, and a plurality of word line driver circuits coupledto the voltage source, many of which are deselected, and one or a few ofwhich are selected in a given access to the array. The memory array hasa plurality of word lines coupled to memory cells in the array. Theplurality of address inputs is adapted to receive addresses identifyingselected memory cells in the array. The voltage source supplies avoltage. The decoder selects a selected word line driver circuit. Thedeselected word line driver circuits capacitively load the voltagesource. One or more word line driver circuits in the plurality of wordline driver circuits respectively include a driver circuit, a feedbackcircuit, and a load reduction circuit. The driver circuit has an input,two power inputs, and an output. The output is coupled to a word line.The first power input is coupled to the voltage source. In a selectedmode, the word line driver circuit couples the word line to the firstpower input. In a deselected mode, the word line driver circuit couplesthe word line to the second power input, which receives typically aground potential or other reference potential. The feedback circuit hasan input, an output, and a power input. The input of the feedbackcircuit is coupled to the output of the driver circuit. The power inputof the feedback circuit is coupled to the voltage source. The loadreduction circuit has an input, an output, and a control input. Theinput of the load reduction circuit is coupled to the output of thefeedback circuit. The output of the load reduction circuit is coupled tothe input of the driver circuit. The load reduction circuit reduces acapacitive load of the driver circuit on the voltage source.

In a third embodiment of the invention, a word line driver circuitincludes a voltage source, a driver circuit, a feedback circuit, and aload reduction circuit. The driver circuit comprises a P-channeltransistor and an N-channel transistor. The P-channel transistorincludes a gate terminal, a first terminal coupled to the voltagesource, and a second terminal adapted for connection to a word line. TheN-channel transistor includes a gate terminal, a first terminal, and asecond terminal coupled to the second terminal of the P-channeltransistor. In a selected mode, the word line driver circuit couples theword line to the voltage source. In a deselected mode, the word linedriver circuit couples the word line to a reference potential of thefirst terminal of the N-channel transistor. The feedback circuitcomprises a P-channel transistor. The P-channel transistor includes agate terminal coupled to the second terminal of the N-channel transistorof the driver circuit, a first terminal coupled to the voltage source,and a second terminal coupled to the gate of the P-channel transistor ofthe driver circuit. The load reduction circuit comprises an N-channeltransistor. The N-channel transistor includes a control terminal, afirst terminal coupled to the second terminal of the P-channeltransistor of the feedback circuit, and a second terminal coupled to thegate of the N-channel transistor of the driver circuit. In thedeselected mode, the load reduction circuit reduces a capacitive load ofthe driver circuit on the voltage source.

In a fourth embodiment of the invention, an integrated circuit memorydevice includes a memory array, a plurality of address inputs, a voltagesource, a decoder, and a plurality of word line driver circuits coupledto the voltage source, many of which are deselected, and one or a few ofwhich are selected in a given access to that array. The memory array hasa plurality of word lines coupled to memory cells in the array. Theplurality of address inputs is adapted to receive addresses identifyingselected memory cells in the array. The decoder selects a selected wordline driver circuit. The deselected word line driver circuitscapacitively load the voltage source. The word line driver circuits inthe plurality of word line driver circuits respectively include a drivercircuit, a feedback circuit, and a load reduction circuit. The drivercircuit comprises a P-channel transistor and an N-channel transistor.The P-channel transistor includes a gate terminal, a first terminalcoupled to the voltage source, and a second terminal adapted forconnection to a word line. The N-channel transistor includes a gateterminal, a first terminal, and a second terminal coupled to the secondterminal of the P-channel transistor. In a selected mode, the word linedriver circuit couples the word line to the voltage source. In adeselected mode, the word line driver circuit couples the word line to areference potential of the first terminal of the N-channel transistor.The feedback circuit comprises a P-channel transistor. The P-channeltransistor includes a gate terminal coupled to the second terminal ofthe N-channel transistor of the driver circuit, a first terminal coupledto the voltage source, and a second terminal coupled to the gate of theP-channel transistor of the driver circuit. The load reduction circuitcomprises an N-channel transistor. The N-channel transistor includes acontrol terminal, a first terminal coupled to the second terminal of theP-channel transistor of the feedback circuit, and a second terminalcoupled to the gate of the N-channel transistor of the driver circuit.In the deselected mode, the load reduction circuit reduces a capacitiveload of the driver circuit on the voltage source.

Further, a method for lowering current consumption for the abovementioned word line driver circuit in a deselected mode according to hisinvention comprises the acts of:

coupling a driver circuit to a feedback circuit to pass a voltageprovided by a voltage source through the feedback circuit to an input ofthe driver circuit in the deselected mode; and

reducing a capacitive load of the driver circuit on the voltage source.

Other aspects and advantages of the present invention can be seen uponreview of the figures, the detailed description, and the claims whichfollow.

BRIEF DESCRIPTION OF THE FIGURES

These and other features and advantages of the present invention willbecome more apparent to those skilled in the art from the followingdetailed description in conjunction with the appended drawings in which:

FIG. 1 is a block diagram of an integrated circuit memory deviceincluding the enhanced word line driver of the present invention.

FIG. 2 is a block diagram of the x-decoder in the system of FIG. 1.

FIG. 3 is a block diagram of the AVX switches and the enhanced word linedrivers and decoders in the system of FIG. 2.

FIG. 4 is a simplified diagram of the AVX switch in the system of FIG.3.

FIGS. 5A and 5B illustrate prior art word line drivers.

FIGS. 6A, 6B, 6C and 6D illustrate implementations of the enhanced wordline driver in the system of FIG. 3.

FIGS. 7A and 7B are graphs illustrating improvements in an integratedcircuit memory device resulting from implementing the enhanced word linedriver.

DETAILED DESCRIPTION

The detailed description of the preferred embodiments of the presentinvention is provided with respect to FIGS. 1-7. FIG. 1 provides anoverview of a flash memory device incorporating an enhanced word linedriver to reduce the capacitive for low voltage applications.

FIG. 1 illustrates an integrated circuit 100 featuring a flash array101. In other embodiments the flash array 101 may be another memorytype, such as volatile memory, EPROM, FF-EEPROM, NOVRAM, or FRAM. Theintegrated circuit 100 includes external control inputs 102 coupled to acontrol input logic 104. Control input logic 104 is coupled to a writestate machine 106, a command data latch 108, and an address latch andbuffer 110. The command data latch 108 is coupled to a command datadecoder 112. The command data decoder 112 is coupled to a commandinterface register 114. The command interface register 114 is coupled tothe write state machine 106. The write state machine 106 is coupled to aprogram/erase high voltage 116 and a page program data latch 118. Thepage program data latch 118 accepts data from an I/O buffer 134.

The integrated circuit 100 further includes a set of address inputs 120coupled to the address latch and buffer 110. Addresses buses 122 couplethe address latch and buffer 110 to an x-decoder 124 and a y-decoder126. The x-decoder 124 comprises drivers with reduced load in deselectedmode 127. The output of the program/erase high voltage 116 is coupled tothe x-decoder 124, the flash array 101, and a program data high voltage128. The program data high voltage is coupled to the page program datalatch 118 and a y-pass gate 130. The y-pass gate is coupled to a senseamplifier 132. The sense amplifier 132 is coupled to the I/O buffer 134.The I/O buffer 134 is coupled to a data bus 136 that leads off theintegrated circuit via a plurality of data in/data out connections 138.The voltage boost 140, which comprises a charge pump in one embodiment,receives an off chip voltage VDD 142 and provides boosted and nonboostedvoltages to the x-decoder 124. Voltage boost 140 is comprised in thex-decoder 124, and is shown separately in the heuristic FIG. 1.

The control input logic 104 is set in motion by external control inputs102 that include, for example, write enable, output enable, writeprotect, and byte enable. Write state machine 106 eases the load on amicroprocessor outside the integrated circuit 100 by cyclingautomatically through many erase or program steps. The program/erasehigh voltage 116 supplies the x-decoder 124, an array source highvoltage to the flash array 101 for erase operations, and the programdata high voltage 128 for program operations.

The page program data latch 118 implements page program mode, minimizingprogramming time. The I/0 buffer 134 receives data from, and sends datato, the outside of the integrated circuit via the data bus 136. The I/0buffer sends data to be programmed to the page program data latch 118and receives data to be sent outside the integrated circuit 100 from thesense amplifier 132. The sense amplifier 132, upon receiving data fromthe flash array 101 through the y-pass gate 130, improves access speeds.

The address latch and buffer 110 accepts input from the set of addressinputs 120. Addresses are sent via address buses 122 to the x-decoder124 and the y-decoder 126 to access memory cells in the flash array 101.

FIG. 2 shows a more detailed view of the x-decoder 124 from FIG. 1.Address buses 122 carry memory addresses to word line predecoders 202and an address transition detection circuit 204. The address detectioncircuit 204 couples to a word line boost voltage generator 206. The wordline boost voltage generator 206 is coupled to node 207, carrying signalAVX. Node 207 is coupled to AVX switches 208. AVX switches 208 arecoupled to enhanced word line drivers and decoders 210. The enhancedword line drivers and decoders 210 are coupled to word line predecoders202 and to word lines 212 included in the flash array 101.

Word line predecoders 202 generate signals that select a particularsection within the enhanced word line drivers and decoders 210. Addresstransition detection 204 generates select signals that indicatetransitions between word lines 212.

The word line boost voltage generator 206 adapts the integrated circuit100 to function with a supply voltage external to the integratedcircuit, over a range of about 2.7 to 3.6 volts. One embodiment of theword line boost voltage generator 206 comprises a charge pump. Theexternal supply voltage is boosted to an on chip voltage useful for onchip operations. For example, word lines that supply a gate potential toflash memory cells are designed to operate at a read voltage of 4 voltsor more. The boosted or nonboosted voltage is sent as signal AVX to AVXswitches 208. AVX switches 208 in turn couple to sections of word linedrivers within enhanced word line drivers and decoders 210.

FIG. 3 shows more detailed views of AVX switches 208 and enhanced wordline drivers and decoders 210 from FIG. 2. Decoders within enhanced wordline drivers and decoders 210 are not included in FIG. 3. AVX switches208 comprise eight switches, AXP#0 to AVXP#7, receiving input from node207 carrying signal AVX. Only AVXP#0 302, AVXP#1 304, and AVXP#7 306 areshown in FIG. 3. Enhanced word line drivers and decoders 210 comprise2048 word line drivers, divided into eight sections of 256 word linedrivers each. FIG. 3 shows only three of the eight sections, section308, section 310, and section 312, each comprising 256 word linedrivers. Section 308 comprises enhanced word line driver 0 to enhancedword line driver 255, for example enhanced word line driver 0, 314,enhanced word line driver 1, 316, and enhanced word line driver 255,318. Section 310 comprises enhanced word line driver 256 to enhancedword line driver 511, for example enhanced word line driver 256, 320,and enhanced word line driver 511, 322. Section 312 comprises enhancedword line driver 1792 to enhanced word line driver 2047, for exampleenhanced word line driver 1792, 324, and enhanced word line driver 2047,326. Each enhanced word line driver is coupled to one or more word linesincluded in word lines 212. Enhanced word line driver 0, 314 is coupledto word line 0, 328. Enhanced word line driver 1, 316 is coupled to wordline 1, 330. Enhanced word line driver 255, 318, is coupled to word line255, 332. Enhanced word line driver 256, 320, is coupled to word line256, 334. Enhanced word line driver 511, 322, is coupled to word line511, 336. Enhanced word line driver 1792, 324, is coupled to word line1792, 338 Enhanced word line driver 2047, 326 is coupled to word line2047, 340.

Node 342 between AVXP#0 302 and section 308 carries signal AVXP0. Node344 between AVXP#1 304 and section 310 carries signal AVXP1. Node 346between AVXP#7 and section 312 carries signal AVXP7. One of the eightswitches AVXP#0 to AVXP#7 is selected, causing one of the eight 256 wordline driver sections, such as one of section 308, section 310, andsection 312, to load the word line boost voltage generator 206. WhenAVXP#0 302 is selected, section 308 with enhanced word line driver 0 toenhanced word line driver 255 loads the word line boost voltagegenerator 206. In the remaining discussion, AVXP#0 302 is selected andthe other AVX switches, for example AVXP#1 304 and AVXP#7 306, aredeselected. In the remaining discussion, enhanced word line driver 0,314, is selected, and the remaining 2047 enhanced word line drivers,from enhanced word line driver 1, 316, to enhanced word line driver2047, 326, are deselected.

The word line boost voltage generator 206 suffers capacitive loadingfrom deselected word line drivers. Capacitive loading lengthens thevoltage boost time and increases power consumption. When AVXP#0 302 isselected and enhanced word line driver 0, 314, is selected, 255deselected enhanced word line drivers, including deselected enhancedword line driver 1, 316, and deselected enhanced word line driver 255,318, capacitively load the word line boost voltage generator 206. Thepresent invention decreases the capacitive loading of deselected wordline drivers on the word line boost voltage generator 206, shorteningthe voltage boost time and decreasing power consumption. The shortenedvoltage boost time speeds read operations on the selected word line 0,328.

FIG. 4 shows a more detailed view of AVXP#0 302. Transistors having athick gate oxide are indicated with a circuit symbol including arectangle for the gate terminal. Transistors having a thick gate oxideare: 416, 418, and 424. NAND gate 401 has two inputs, node 402 carryingsignal ENSW and node 403 carrying signal XBL4IB. Signal XBL4IB is sentfrom the decoder to select one of the eight wordline driver sections.ENSW is an enabling signal. NAND gate 401 is coupled to node SELK 404.Level shifter 406 has two inputs, IN 408 and SWPWR 410. Input SWPWR 410is coupled to WELLSW, a voltage source for the level shifter 406. InputIN 408 is coupled to node SELK 404. Level shifter 406 has two outputs,OUT 412 and OUTB 414. P-channel transistor 416 has a gate coupled to OUT412, a source coupled to supply voltage VDD 417, and a drain coupled tonode 342. P-channel transistor 418 has a gate coupled to OUTB 414, asource coupled to node 207 carrying signal AVX, and a drain coupled tonode 342. The two inputs to NAND gate 420 are node SELK 404 and node 419carrying signal AVX0, a signal allowing node 342 to discharge to ground426. NAND gate 420 is coupled to inverter 422. N-channel transistor 424has a gate coupled to inverter 422, a source coupled to ground 426, anda drain connected to node 342. The output of AVXP#0 302 is signal AVXP0on node 342. AVXP#0 302 couples and decouples the word line boostvoltage generator 206 to section 308. Consequently, AVXP#0 302 couplesand decouples the word line boost voltage generator 206 to the parasiticcapacitances of section 308.

When level shifter 406 input IN 408 is low, OUT 412 outputs low and OUTB414 outputs the signal on SWPWR 410. When level shifter 406 input IN 408is high, OUT 412 outputs the signal on SWPWR 410 and OUTB 414 outputslow.

FIG. 5A shows prior art word line driver 500A, comprising a drivercircuit 502 and a feedback circuit 504A. Node 342 supplies signal AVXP0.Node 501 supplies signal PNVB0. Node WLB 506 is an input to the drivercircuit 502 and an output of the feedback circuit 504A. Node 508 is aninput to the feedback circuit 504A and an output of the driver circuit502. Node 508 leads to a word line 510. The driver circuit 502 comprisesP-channel transistor MP1 512 and N-channel transistor MN1 514, eachhaving a gate, a source, and a drain. The gates of P-channel transistorMP1 512 and N-channel transistor MN1 514 are coupled to node WLB 506.The drains of P-channel transistor MP1 512 and N-channel transistor MN1514 are coupled to node 508. The source of P-channel transistor MP1 512is coupled to node 342. The source of N-channel transistor MN1 514 iscoupled to node 501. The feedback circuit 504A comprises P-channeltransistor MP2 516 and N-channel transistor MN2 518, each having a gate,a source, and a drain. The gates of P-channel transistor MP2 516 andN-channel transistor MN2 518 are coupled to node 508. The drains ofP-channel transistor 516 and N-channel transistor MN2 518 are coupled tonode WLB 506. The source of P-channel transistor MP2 516 is coupled tonode 342. The source of N-channel transistor MN2 518 is coupled to node501.

Node WLB 506 controls whether the word line driver 500A and the wordline 510 are selected or deselected. The operation of the word linedriver 500A comprising driver circuit 502 and feedback circuit 504A iswell known to those skilled in the art. When node WLB 506 is low, theword line driver 500A is in selected mode and the word line 510 iscoupled to node 342 providing signal AVXP0; word line 510 is selected.When node WLB 506 is high, the word line driver 500A is in deselectedmode and the word line 510 is coupled to node 501 providing signalPNVB0; the word line 510 is deselected.

When word line driver 500A is in deselected mode and word line 510 isdeselected, driver circuit 502 couples node 508 to node 501 throughN-channel transistor MN1 514, and feedback circuit 504A couples node 342to the gates of P-channel transistor MP1 512 and N-channel transistorMN1 514 through P-channel transistor MP2 516. Thus, when prior art wordline driver 500A is in deselected mode, node 342 carrying signal AVXP0is coupled to the gate capacitance of N-channel transistor MN1 514.Thus, node 342 is loaded with the gate capacitance of N-channeltransistor MN1 514. Node 342 is also loaded with the capacitance ofP-channel transistor MP1 512, which in deselected mode includes anoverlap capacitance smaller than the gate capacitance of N-channeltransistor MN1 514. When the word line boost voltage generator 206outputs the signal AVX on node 207, the voltage of the gate oftransistor MN1 514 reaches a corresponding voltage. For example, ifsignal AVX on node 207 provides some nonboosted voltage in the range ofabout 2.7 to 3.6 volts, in deselected word line driver 500A the voltageof the gate of transistor MN1 514 rises to a comparable nonboostedvoltage in the range of about 2.7 to 3.6 volts. In another example, ifsignal AVX on node 207 provides some boosted voltage of 4 volts or morein preparation for a read operation to access flash array 101, indeselected word line driver 500A the voltage of the gate of transistorMN1 514 rises to a comparable boosted voltage of 4 volts or more.Because 255 deselected word line drivers are coupled to node 342, thegate capacitance of N-channel transistor MN1 514 in each deselected wordline driver cumulatively contributes to significantly increased powerconsumption and lengthened voltage boost times. In normal operation,there are many deselected word line drivers and only one selected wordline driver.

FIG. 500B shows a prior art word line driver 500B. Prior art word linedriver 500B is structurally similar to prior art word line driver 500Aexcept for a feedback circuit 504B, which does not include N-channeltransistor MN2 518. The operation of prior art word line driver 500B,comprising driver circuit 502 and feedback circuit 504B, is well knownto those skilled in the art. Word line driver 500B suffers the samecapacitive loading problems as the word line driver 500A.

FIGS. 6A, 6B, 6C, and 6D show various embodiments of the presentinvention. The enhanced word line drivers 600A, 600B, 600C, and 600D aresome of the possible embodiments of, for example, enhanced word linedriver 1, 316, and enhanced word line driver 255, 318. FIGS. 6A, 6B, 6C,and 6D indicate transistors having a thick gate oxide with a circuitsymbol including a rectangle for the gate terminal. Transistors having athick gate oxide are: 612, 614, 616, 618, 622, 628, 630, and 632.N-channel transistors having a lower threshold voltage due to maskingduring implantation of extra p-type impurities are indicated with acircuit symbol including a hatched area. Transistors having a lowerthreshold voltage are: 622, 628, 630, and 632. N-channel transistorshaving a triple well structure are indicated with a circled circuitsymbol. Transistors having a triple well structure are: 614, 618, 622,and 628.

FIG. 6A shows enhanced word line driver 600A, comprising a drivercircuit 602, a feedback circuit 604A, and a load reduction circuit 620A.Node 342 supplies signal AVXP0. Node 601 supplies signal PNVB0. Node WLB606 is an output of the feedback circuit 604A. Node 608 is an input tothe feedback circuit 604A and an output of the driver circuit 602. Node608 is coupled to a word line 610. The driver circuit 602 comprisesP-channel transistor MP1 612 (w=36 μm,1=0.75 μm) and N-channeltransistor MN1614 (w=63 μm,1=0.8 μm), each having a gate, a source, anda drain. The gates of P-channel transistor MP1 612 and N-channeltransistor MN1 614 are coupled to node WLB 606. The drains of P-channeltransistor MP1 612 and N-channel transistor MN1 614 are coupled to node608. The source of P-channel transistor MP1 612 is coupled to node 342.The source of N-channel transistor MN1 614 is coupled to node 601. Thefeedback circuit 604A comprises P-channel transistor MP2 616 (w=2.0μm,=1.5 μm) and N-channel transistor MN2 618 (=3.35 μm, 1=2.1 μm), eachhaving a gate, a source, and a drain. The gates of P-channel transistorMP2 616 and N-channel transistor MN2 618 are coupled to node 608. Thedrains of P-channel transistor 616 and N-channel transistor MN2 618 arecoupled to node WLB 606. The source of P-channel transistor MP2 616 iscoupled to node 342. The source of N-channel transistor MN2 618 iscoupled to node 601.

The input of word line driver 600A is coupled to decoder circuitry 626.The decoder circuitry 626 comprises N-channel transistors 628, 630, and632. N-channel transistor MN3 628 (w=15.5 μm,=1.1 μm) comprises a gatecoupled to node 634 carrying signal NVSX, a source coupled to node 606,and a drain. N-channel transistor M2 630 (w=12 μm,1=1.3 μm) comprises agate coupled to node 636 carrying signal XRB, a drain coupled to node637 providing a voltage VDD, and a source coupled to the drain ofN-channel transistor MN3 628. N-channel transistor M1 632 (w=24 μm,=1.1μm) comprises a gate coupled to node 638 carrying signal XR, a draincoupled to node 640 carrying signal IN, and a source coupled to thedrain of N-channel transistor MN3 628. VDD is typically the same voltageas the off chip supply voltage. Signal NVSX is sent from the voltageselector circuitry, not shown, and signals IN, XR, and XRB are sent fromthe decoder, not shown.

In this preferred embodiment, the load reduction circuit 620A comprisesa voltage source 624 providing a voltage VDD, and an N-channeltransistor MN4 622 (w=15.5 μm,1=1.1 μm) including a gate coupled to thevoltage source 624, a drain coupled to node WLB 606, and a sourcecoupled to the gate of transistor MN1 614. VDD is typically the samevoltage as the off chip supply voltage.

Node WLB 606 controls whether the word line driver 600A and the wordline 610 are selected or deselected. When node WLB 606 is low, the wordline driver 600A is in selected mode and the word line 610 is coupled tonode 342 providing signal AVXP0; word line 610 is selected. Signal AVXP0has a boosted voltage or a nonboosted voltage, depending on the outputof word line boost voltage generator 206. When node WLB 606 is high, theword line driver 600A is in deselected mode and the word line 610 iscoupled to node 601 providing signal PNVB0; the word line 610 isdeselected.

When word line driver 600A is in deselected mode and word line 610 isdeselected, driver circuit 602 couples node 608 to node 601 throughN-channel transistor MN1 614, and feedback circuit 604A couples node 342to the gate of P-channel transistor MP1 612 and to node WLB 606 throughP-channel transistor MP2 616. Thus, when word line driver 600A is indeselected mode, node 342 carrying signal AVXP0 is coupled to node WLB606. Node 342 is coupled through load reduction circuit 620A to the gateof N-channel transistor MN1 614. Node 342 is loaded with the capacitanceof P-channel transistor MP1 612, which in deselected mode is an overlapcapacitance smaller than the gate capacitance of N-channel transistorMN1 614.

Prior to selection of one of the eight 256 word line driver sections,such as section 308, signal AVXP0 342 is set to the voltage VDD. Thevoltage boost circuitry will not be activated until the decodingcircuitry 626 has completed decoding operations and the selected wordline, such as word line 328, has reached a certain voltage level, forexample the voltage VDD or a voltage a little less than VDD. Thus, priorto the voltage boost operation, the source of N-channel transistor MN4622, coupled to the gate of N-channel transistor MN1 614, reaches avoltage level equal to the voltage VDD minus a threshold voltage ofN-channel transistor MN4 622. By delaying the activation of the voltageboost circuitry, none of the boost energy will be wasted during wordline transitions.

When the enhanced word line driver 600A is in deselected mode, therelationship between the voltage of signal AVX carried voltage VDD prodthe voltage VDD provided by voltage source 624 determines the degree towhich the load reduction circuit 620A couples or decouples thecapacitance. When a gate to source voltage of N-channel transistor MN4622 exceeds the threshold voltage of N-channel transistor MN4 622, loadreduction circuit 620A fully couples the gate capacitance of N-channeltransistor MN1 614 to node WLB 606. Once the voltage boost operationstarts, the voltage at the gate of N-channel transistor MN1 614 stays atthe voltage level equal to the voltage VDD minus the threshold voltageof N-channel transistor MN4 622, and the gate capacitance of N-channeltransistor MN1 614 is decoupled from the word line boost voltagegenerator 206.

In the preferred embodiment, a magnitude of the threshold voltage isminimized in order to effectively turn on N-channel transistor MN1 614when the word line driver is in a deselected state. Thus, the thresholdvoltage of N-channel transistor MN4 622 is less than the typicalthreshold of other transistors in the word line driver circuit, forexample, N-channel transistor MN1 614. The threshold voltage oftransistor MN4 622 in this example is about 0.3 volts. The thresholdvoltage of transistor MN1 614 is about 0.6 volts in this example. Thethreshold voltage can be adjusted by, for example, ion implantation intothe channel region of a transistor.

For example, in one embodiment the threshold voltage of transistor MN4622 is about 0.3 volts, the voltage source 624 provides a voltage VDD ina range of about 2.7 to 3.6 volts, for example 2.8 volts, and signalAVXP0 provides one of a nonboosted voltage of 2.8 volts and a boostedvoltage of about 4.0 volts, a voltage necessary for a read operation.VDD is typically the same voltage as the off chip supply voltage. Whendeselected word line driver 600A receives signal AVXP0 that provides thenonboosted voltage of 2.8 volts, the load reduction circuit 620A couplessignal AVXP0 to the gate of N-channel transistor MN1 614 and the gate oftransistor MN1 614 rises to about 2.5 volts, sufficient to effectivelyturn on N-channel transistor MN1 614. When deselected word line driver600A then receives a signal AVXP0 that provides the boosted voltage ofabout 4.0 volts, the voltage at the gate of transistor MN1 614 remainsat about 2.5 volts. The load reduction circuit 620A decouples the signalAVX from the gate capacitance of transistor MN1 614. For simplicity ofexplanation, the above example does not take into account the bodyeffect of N-channel transistor MN1 622, so the 2.5 volt figure isactually too high.

FIG. 6B shows another embodiment of the present invention, showingenhanced word line driver 600B. Enhanced word line driver 600B issimilar to enhanced word line driver 600A, but comprises a loadreduction circuit 620B and feedback circuit 604B. Load reduction circuit620B comprises an N-channel transistor 622, including a gate coupled tovoltage source 624, a source coupled to node WLB 606, and a draincoupled to the drain of P-channel transistor MP2 616. The channel widthand length dimensions for transistors in FIG. 6B are similar to thedimensions given in the discussion of FIG. 6A above, except fortransistors 622 (w=24 μm,1=1.1 μm) and 628 (w=24 μm,1=1.1 μm).

FIG. 6C shows another embodiment of the present invention, showingenhanced word line driver 600C. Enhanced word line driver 600C issimilar to enhanced word line driver 600A, but lacks N-channeltransistor MN2 618.

FIG. 6D shows another embodiment of the present invention, showingenhanced word line driver 600D. Enhanced word line driver 600D issimilar to enhanced word line driver 600B, but lacks N-channeltransistor MN2 618.

In another embodiment, signal AVX may be decoupled from the gatecapacitance of transistor MN1 614 in connection with another operation,such as erase or program.

In another embodiment, an enhanced word line driver comprises a loadreduction circuit which allows part of the VDD energy to precharge thegate of N-channel transistor MN1 614 before the voltage boostingoperation, so that N-channel transistor MN1 614 is on, signal PNVB0 iscoupled to the word line 610 in a deselected state, and the circuitrydoes not need to charge the gate capacitance during the followingvoltage boost.

Other possible embodiments of the present invention include but are notlimited to an enhanced word line driver that couples a word line to anegative voltage for read operations, an enhanced word line drivercomprising a load reduction circuit including a P-channel transistor,and other reconfigurations obvious to those skilled in the art.

FIGS. 7A and 7B show word line timing waveforms in response to selecteddecoding signals and compare operation of an integrated circuit memorydevice with and without the present invention. Waveform 702 indicatesoutput of a prior art selected word line driver. Waveform 704 indicatesoutput of a selected enhanced word line driver, for example enhancedword line driver 0 314. Waveform 704 rises faster as a result of lesscapacitive loading from deselected word line drivers. FIG. 7A showstiming waveforms for an integrated circuit memory device with anonboosted voltage of 3.7 volts at a temperature of -40 degrees C. InFIG. 7A, the selected word line driver provides a read mode voltage witha speed enhancement of about 5 nanoseconds. FIG. 7B shows timingwaveforms for an integrated circuit memory device with a nonboostedvoltage of 2.6 volts at a temperature of 85 degrees C. In FIG. 7B, theselected word line driver provides a read mode voltage with a speedenhancement of about 9 nanoseconds. The lower the nonboosted voltage,the more improvement the enhanced word line driver will make.

The foregoing description of preferred embodiments of the invention hasbeen presented for the purposes of illustration and description. It isnot intended to be exhaustive or to limit the invention to the preciseforms disclosed. Obviously many modifications and variations will beapparent to practitioners skilled in this art. It is intended that thescope of the invention be defined by the following claims and theirequivalents.

What is claimed is:
 1. A word line driver circuit comprising:a voltagesource supplying a first voltage; a driver circuit including an input, afirst power input, a second power input, and an output, and the outputcoupled to a word line, and the first power input coupled to the voltagesource, and the word line driver circuit in a selected mode coupling theword line to the first power input, and the word line driver circuit ina deselected mode coupling the word line to the second power input; afeedback circuit including an input, an output, and a power input, andthe input of the feedback circuit coupled to the output of the drivercircuit, and the power input of the feedback circuit coupled to thevoltage source; and a load reduction circuit, including an input, anoutput, and a control input, and the input of the load reduction circuitcoupled to the output of the feedback circuit, and the output of theload reduction circuit coupled to the input of the driver circuit, andin the deselected mode the load reduction circuit reducing a capacitiveload of the driver circuit on the voltage source.
 2. The word linedriver circuit of claim 1, wherein the load reduction circuit comprisesa transistor including a control terminal, a first terminal, and asecond terminal, and the control terminal coupled to the control inputof the load reduction circuit, and the first terminal coupled to theinput of the load reduction circuit, and the second terminal coupled tothe output of the load reduction circuit.
 3. The word line drivercircuit of claim 2, wherein the driver circuit includes a transistor,and the transistor of the driver circuit has a threshold voltage, andthe transistor of the load reduction circuit includes a thresholdvoltage, and the threshold voltage of the transistor of the loadreduction circuit has a magnitude less than a magnitude of the thresholdvoltage of the transistor device included in the driver circuit.
 4. Theword line driver circuit of claim 1, wherein the control input of theload reduction circuit is coupled to a second voltage source, and thesecond voltage source providing a second voltage.
 5. The word linedriver circuit of claim 4, wherein the second voltage has a magnitudeless than a magnitude of the first voltage.
 6. The word line drivercircuit of claim 1, wherein the driver circuit comprises an inverter. 7.The word line driver circuit of claim 1, wherein the feedback circuitcomprises a transistor.
 8. The word line driver circuit of claim 1,wherein the feedback circuit comprises an inverter.
 9. The word linedriver circuit of claim 1, wherein the first voltage is for a readoperation.
 10. The word line driver circuit of claim 1, wherein thevoltage source comprises a charge pump.
 11. A word line driver circuitcomprising:a voltage source; a driver circuit comprising:a P-channeltransistor including a gate terminal, a first terminal coupled to thevoltage source, and a second terminal adapted for connection to a wordline; and an N-channel transistor including a gate terminal, a firstterminal, and a second terminal coupled to the second terminal of theP-channel transistor, wherein the word line driver circuit in a selectedmode couples the word line to the voltage source, and the word linedriver circuit in a deselected mode couples the word line to a referencepotential of the first terminal of the N-channel transistor; a feedbackcircuit comprising:a P-channel transistor including a gate terminalcoupled to the second terminal of the N-channel transistor of the drivercircuit, a first terminal coupled to the voltage source, and a secondterminal coupled to the gate of the P-channel transistor of the drivercircuit; and a load reduction circuit comprising:an N-channel transistorincluding a control terminal, a first terminal coupled to the secondterminal of the P-channel transistor of the feedback circuit, and asecond terminal coupled to the gate of the N-channel transistor of thedriver circuit, wherein in the deselected mode the load reductioncircuit reduces a capacitive load of the driver circuit on the voltagesource.
 12. The word line driver circuit of claim 11, wherein thefeedback circuit further comprises:an N-channel transistor including agate terminal coupled to the second terminal of the N-channel transistorof the driver circuit, a first terminal coupled to the referencepotential, and a second terminal coupled to the gate of the P-channeltransistor of the driver circuit.
 13. An integrated circuit memorydevice, comprising:a memory array, including a plurality of word linescoupled to memory cells in the array; a plurality of address inputsadapted to receive addresses identifying selected memory cells in thearray; a voltage source supplying a first voltage; a plurality of wordline driver circuits, and the plurality of word line driver circuitscapacitively loading the voltage source, and one or more word linedriver circuits in the plurality of word line driver circuitscomprising:a driver circuit including an input, a first power input, asecond power input, and an output, and the output coupled to a wordline, and the first power input coupled to the voltage source, and theword line driver circuit in a selected mode coupling the word line tothe first power input, and the word line driver circuit in a deselectedmode coupling the word line to the second power input; a feedbackcircuit including an input, an output, and a power input, and the inputof the feedback circuit coupled to the output of the driver circuit, andthe power input of the feedback circuit coupled to the voltage source;and a load reduction circuit, including an input, an output, and acontrol input, and the input of the load reduction circuit coupled tothe output of the feedback circuit, and the output of the load reductioncircuit coupled to the input of the driver circuit, and in thedeselected mode the load reduction circuit reducing a capacitive load ofthe driver circuit on the voltage source; and a decoder selecting one ormore word line driver circuits in the plurality of word line drivercircuits.
 14. The integrated circuit memory device of claim 13, whereinthe load reduction circuit comprises a transistor including a controlterminal, a first terminal, and a second terminal, and the controlterminal coupled to the control input of the load reduction circuit, andthe first terminal coupled to the input of the load reduction circuit,and the second terminal coupled to the output of the load reductioncircuit.
 15. The integrated circuit memory device of claim 14, whereinthe driver circuit includes a transistor, and the transistor of thedriver circuit has a threshold voltage, and the transistor of the loadreduction circuit includes a threshold voltage, and the thresholdvoltage of the transistor of the load reduction circuit has a magnitudeless than a magnitude of the threshold voltage of the transistor deviceincluded in the driver circuit.
 16. The integrated circuit memory deviceof claim 13, wherein the control input of the load reduction circuit iscoupled to a second voltage source, and the second voltage sourceproviding a second voltage.
 17. The integrated circuit memory device ofclaim 16, wherein the second voltage has a magnitude less than amagnitude of the first voltage.
 18. The integrated circuit memory deviceof claim 13, wherein the driver circuit comprises an inverter.
 19. Theintegrated circuit memory device of claim 13, wherein the feedbackcircuit comprises a transistor.
 20. The integrated circuit memory deviceof claim 13, wherein the feedback circuit comprises an inverter.
 21. Theintegrated circuit memory device of claim 13, wherein the first voltageis for a read operation.
 22. The integrated circuit memory device ofclaim 13, wherein the voltage source comprises a charge pump.
 23. Anintegrated circuit memory device, comprising:a memory array, including aplurality of word lines coupled to memory cells in the array; aplurality of address inputs adapted to receive addresses identifyingselected memory cells in the array; a voltage source; a plurality ofword line driver circuits, and the plurality of word line drivercircuits capacitively loading the voltage source, and one or more wordline driver circuits in the plurality of word line driver circuitscomprising: a driver circuit comprising:a P-channel transistor includinga gate terminal, a first terminal coupled to the voltage source, and asecond terminal adapted for connection to a word line; and an N-channeltransistor including a gate terminal, a first terminal, and a secondterminal coupled to the second terminal of the P-channel transistor,wherein the word line driver circuit in a selected mode couples the wordline to the voltage source, and the word line driver circuit in adeselected mode couples the word line to a reference potential of thefirst terminal of the N-channel transistor; a feedback circuitcomprising:a P-channel transistor including a gate terminal coupled tothe second terminal of the N-channel transistor of the driver circuit, afirst terminal coupled to the voltage source, and a second terminalcoupled to the gate of the P-channel transistor of the driver circuit;and a load reduction circuit comprising:an N-channel transistorincluding a control terminal, a first terminal coupled to the secondterminal of the P-channel transistor of the feedback circuit, and asecond terminal coupled to the gate of the N-channel transistor of thedriver circuit, wherein in the deselected mode the load reductioncircuit reduces a capacitive load of the driver circuit on the voltagesource; and a decoder selecting one or more word line driver circuits inthe plurality of word line driver circuits.
 24. The integrated circuitmemory device of claim 23, wherein the feedback circuit furthercomprises:an N-channel transistor including a gate terminal coupled tothe second terminal of the N-channel transistor of the driver circuit, afirst terminal coupled to the reference potential, and a second terminalcoupled to the gate of the P-channel transistor of the driver circuit.25. A method for lowering current consumption from a voltage source fora word line driver circuit in a deselected mode, the method comprisingthe acts of:coupling a driver circuit to a feedback circuit to pass avoltage provided by the voltage source through the feedback circuit toan input of the driver circuit in the deselected mode; and reducing acapacitive load of the driver circuit on the voltage source.
 26. Themethod of claim 25, wherein the reducing act further comprises the actsof:coupling the feedback circuit to the input of the driver circuit witha load reduction circuit; and applying a reference voltage to a controlinput of the load reduction circuit, and the reference voltage having amagnitude less than a magnitude of the voltage provided by the voltagesource, whereby the load reduction circuit transitions from a state ofcoupling a capacitance of the driver circuit to the voltage source to astate of decoupling the capacitance of the driver circuit from thevoltage source.